1. Technical Field
The present disclosure relates to a semiconductor device and, more particularly, to a semiconductor device having a semiconductor chip bonded to an external connection pad by flip-chip bonding and an underfill resin.
2. Background Art
FIG. 1 is a cross sectional view of a related-art semiconductor device. In FIG. 1, reference symbol L designates a distance (hereinafter described as “distance J”) between an upper surface 106A of a substrate 106 and a semiconductor chip 102.
By reference to FIG. 1, a related-art semiconductor device 100 has a wiring board 101, the semiconductor chip 102, and an underfill resin 103. The wiring board 101 has the substrate 106 in which a through hole 107 is formed; a through via 108 formed in the through hole 107; a wiring 109 provided on the upper surface 106A of the substrate 106; and a wiring 111 provided on a lower surface 106B of the substrate 106. The wiring 109 is electrically connected to the wiring 111 by the through via 108.
The semiconductor chip 102 has a plurality of electrode pads 113. Each of the plural electrode pads 113 is provided with an internal connection terminal 114(specifically, e.g., a bump). The electrode pad 113 is electrically connected to the wiring 109 by the internal connection terminal 114. In other words, the semiconductor chip 102 is bonded to the wiring 109 by flip-chip bonding. The distance J between the semiconductor chip 102 and the substrate 106 may be set to 50 μm, for example.
The underfill resin 103 is provided so as to fill a gap between the wiring board 101 and the semiconductor chip 102. The underfill resin 103 is a resin for reinforcing a connection between the electrode pads 113, the wiring 109, and the internal connection terminals 114. The thickness of the underfill resin 103 sandwiched between the substrate 106 and the semiconductor chip 102 may be set to 50 μm, for example.
In the related-art semiconductor device 100 configured as mentioned above, when the thickness of the semiconductor chip 102 and/or the thickness of the substrate 106 are reduced, there arises a problem of warpage occurring in the semiconductor device 100 under the influence of stress of the underfill resin 103. For example, a semiconductor device shown in FIG. 2 is available as a semiconductor device that solves such a problem.
FIG. 2 is a cross sectional view of another related-art semiconductor device. In FIG. 2, constituent elements which are the same as those of the semiconductor device 100 shown in FIG. 1 are assigned the same reference numerals.
By reference to FIG. 2, a related-art semiconductor device 120 has a wiring board 121, semiconductor chips 102 and 125, and the underfill resin 103. The wiring board 121 has a substrate 122, a wiring 123 provided on an upper surface 122A of the substrate 122, and a wiring 124 provided on a lower surface 122B of the substrate 122.
The semiconductor chip 102 is electrically connected to the wiring 123 by internal connection terminals 114 provided on the respective electrode pads 113. The semiconductor chip 102 is bonded to the wiring 123 by flip-chip bonding.
A semiconductor chip 125 has a plurality of electrode pads 126. The plurality of electrode pads 126 has the internal connection terminals 114 (specifically, e.g., bumps), respectively. The electrode pads 126 are electrically connected to the wiring 124 by the internal connection terminals 114. The semiconductor chip 125 is bonded to the wiring 124 by flip-chip bonding.
The underfill resin 103 is provided so as to fill a gap between the upper surface of the wiring board 121 and the semiconductor chip 102 and a gap between the lower surface of the wiring board 121 and the semiconductor chip 125.
As mentioned above, the two semiconductor chips 102 and 125 are arranged opposite to each other with the substrate 122 sandwiched therebetween. The underfill resin 103 is provided between the wiring board 121 and the semiconductor chip 102 and between the wiring board 121 and the semiconductor chip 125. The underfill resin 103 provided on both surfaces of the wiring board 121 are made essentially equal in thickness to each other, thereby canceling the stress of the underfill resin 103 provided on both surfaces of the wiring board 121. Therefore, warpage of the semiconductor substrate 120 attributable to the underfill resin 103 can be diminished (see e.g., Japanese Patent Unexamined Document: JP-A-11-265967).
However, the related-art semiconductor device 120 enables a reduction in the warpage of the semiconductor device 120 attributable to the underfill resin 103. However, since the semiconductor chips 102 and 125 are provided on both surfaces of the wiring board 121, there arises a problem of an increase in the size of the semiconductor device 120.